1. Field of the Invention
The present invention relates to a method for fabricating semiconductor devices, and more particularly, to a method for forming trench isolators in semiconductor devices.
2. Description of the Related Art
As the level of integration of semiconductor memory integrated circuits increases, the conventional LOCOS (local oxidation of silicon) process cannot effectively electrically isolate adjacent devices from each other. Accordingly, a "trench isolation" process was introduced for isolating such devices from each other. However, the conventional trench isolation process frequently results in an "edge dipping" effect in the trench isolator material that causes such problems as degradation of gate oxide layers, a "hump" (or "kink") in transistor characteristic curves, and the instability of transistor operation.
FIGS. 1A to 1C sequentially illustrate the conventional method for forming a trench isolator. Referring to FIG. 1A, a silicon nitride mask layer 2 is formed on a pad oxide layer (not shown) on the surface of a semiconductor substrate 1. The masked substrate 1 is then etched to form a trench 3, and an insulating film is deposited on the silicon nitride layer to fill the trench 3. Then, a planarization-etching process is used to remove the insulating film until the top surface of the silicon nitride mask layer 2 is exposed, so that the insulating film in the trench 3 forms a trench isolator 4.
Referring to FIG. 1B, the silicon nitride mask layer 2 is then removed by an H.sub.3 PO.sub.4 stripping process. After the stripping process, the top surface of the trench isolator 4 projects above the surface of the semiconductor substrate 1 adjacent to the trench 3, that is, above the "active region" of the semiconductor substrate 1, by a thickness t1. The thickness t1, which is typically on the order of 30 to 100 nm, is adjusted as a function of all of the processes, particularly including any erosional wet cleaning processes, that are to be performed on the substrate 1 before any gate deposition steps, such that after all such processes are complete, the top surfaces of the trench isolation layer 4 and the substrate 1 are at the same level, i.e., are coplanar. Thus, the silicon nitride mask layer 2 is not completely removed by the planarization-etching process, and any silicon nitride mask layer 2 remaining on the active region of the substrate 1 can increase the stresses applied to the active region during subsequent manufacturing processes, particularly during any high-temperature annealing processes.
Referring to FIG. 1C, after the silicon nitride layer 2 has been stripped away, a number of photolithographic, cleaning, and other manufacturing processes are typically performed on the substrate 1 for purposes of device fabrication, typically three to six of such iterations, and the cleaning processes involved in these can cause an edge dipping 5 of the trench isolation layer 4, which is about 30 to 100 nm deep. This edge dipping 5 effect must also be taken into consideration in deciding the thickness t1.
As explained by Asanga H. Perera et al. in "Trench Isolation for 0.45 .mu.m Active Pitch and Below", IEDM 95, pp. 28.1.1-28.1.4, 1995, the edge dipping that occurs during formation of a trench isolator may result in the degradation of device characteristics, such as lowered threshold voltages, which can be lowered by as much as 0.1V per 20 nm, "humping" of sub-threshold voltage characteristics, and inferior cut-off characteristics. Such degradation of the device can result in increased power consumption of the device, or in a worst case, can render the device inoperable. Moreover, the lowered threshold voltage and the humping of subthreshold voltage characteristics can make the device's operational characteristics pathologically hypersensitive to even small process changes during device fabrication.